Rainbow Electronics ATmega163L - Manual (Page 29)

ATmega163(L)
29
The Timer/Counter Interrupt Flag Register - TIFR
• Bit 7 - OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output
Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare
match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
•
Bit 6 - TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-
bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt
is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.
•
Bit 5 - ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the
input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logic one to the flag.
•
Bit 4 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1 and the data in OCR1A - Output
Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare
match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1A Compare match Interrupt is executed.
•
Bit 3 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when a compare match occurs between the Timer/Counter1 and the data in OCR1B - Output
Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-
tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare
match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1B Compare match Interrupt is executed.
•
Bit 2 - TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in
SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow
Interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
•
Bit 1 - Res: Reserved Bit
This bit is a reserved bit in the ATmega163 and the read value is undefined.
•
Bit 0 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-
bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt
is executed.
External Interrupts
The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the interrupts will trigger even if
the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external
interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the
MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt
will trigger as long as the pin is held low.
Bit 7 6 5 4 3 2 1 0
$38 ($58) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 - TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial value 0 0 0 0 0 0 x 0