Rainbow Electronics ATmega163L - Manual (Page 8)

ATmega163(L)
8
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
in-system re-programmable Flash memory.
With the jump and call instructions, the whole 8K word address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section (256 to 2048 bytes, see page 115) and
the Application Program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section is allowed only in the Boot program section.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe-
cuted). The 11-bit stack pointer SP is read/write accessible in the I/O space.
The 1024 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory.
The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the
higher the priority.
Figure 6. Memory Maps
$0000
$1FFF
Program Memory
Application Flash Section
Boot Flash Section