Rainbow Electronics ATmega163L - Manual (Page 121)

ATmega163(L)
121
• Bit 2 - PGWRT: Page Write
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the
data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0
are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire page write operation.
•
Bit 1 -PGERS: Page Erase
If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The
page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear
upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the
entire page erase operation.
•
Bit 0 - SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If set together with either ASRE, BLBSET, PGWRT or
PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is set, the follow-
ing SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z
pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is exe-
cuted within four clock cycles. During page erase and page write, the SPMEN bit remains high until the operation is
completed.
Writing any other combination than "10001", "01001", "00101", or "00001" in the lower five bits will have no effect.
Preventing Flash Corruption
During periods of low V
CC
, the Flash can be corrupted because the supply voltage is too low for the CPU and the Flash to
operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions
should be applied.
A Flash corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash
requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply
voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done be enabling
the internal Brown-Out Detector (BOD) if the operating voltage matches the detection level. If not, an external low
V
CC
Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient. The total reset time must be longer thatn the
Flash write time. This can be achieved by holding the external reset, or by selecting a long reset timeout.
2. Keep the AVR core in Power Down Sleep Mode during periods of low V
CC
. This will prevent the CPU from attempt-
ing to decode and execute instructions, effectively protecting the Flash from unintentional writes.
Assembly code example for a Boot Loader
;- the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer (lowest address)
; the first data location in Flash is pointed to by the Z pointer (lowest address)
;- error handling is not included
;- the routine must be placed inside the boot space
; Only code inside boot loader
; section should be read during self-programming.
;- registers used: r0, r1, temp1, temp2, looplo, loophi, spmcrval
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;- It is assumed that the interrupts are disabled
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; page erase
ldi spmcrval, (1<
call Do_spm
; re-enable the Application Section