Grass Valley PDR 200 Service Manual - Manual (Page 43)

Master Enhanced Disk Recorder
PDR200 Service Manual 3-11
GPCI to LPCI Interface
The GPCI bus is interfaced to the LPCI bus through a PCI-PCI bridge chip, which is
PCI Local Bus Specification, Revision 2.1 compliant. The chip provides full support
for delayed transactions for buffering memory reads and has separate posted write,
read data, and delayed transaction queues.The address range and operating
parameters for the chip must be configured through its primary PCI interface, which
is connected to the GPCI bus. The initialization software for the EDR boards and the
Fibre Channel board is contained in the vdrsvc program, which runs on the system
processor.
LPCI to Dual JPEG Interface
The LPCI bus interface to two JPEG channels consists of a PCI slave interface with
two JPEG DMA Controllers implemented in the PCI_JPEG_PLD and two LSI JPEG
CODEC Chip sets, DRAM Controllers, and Block-Raster Controllers. The LPCI -
Dual JPEG interface provides a high bandwidth connection between 2 Serial Video
Channels, JPEG memory buffers, and SCSI and EISA DMA controllers via the Local
PCI Bus.
The JPEG DMA Engine is capable of multiple 8-word transfers, indicated by the
count value, between JPEG memory buffers and the LSI JPEG Codecs. DMA control
bits indicate whether the transfer is for Record, Playback or Init Table transfers. Upon
completion or upon encountering an error, the JPEG DMA engines send an interrupt
to the RTP.
LPCI to SCSI Interfaces
The EDR boards provide two 16-bit differential SCSI interfaces which are capable of
supporting SCSI-1, SCSI-2, and Fast-20 SCSI standards.
With the Fast-20 extension, the EDR’s SCSI bus bandwidth increases to a maximum
of 40 MBytes/second when Fast-20 compatible disks are used. The on-board SCSI
terminators, which software can enable, means that external SCSI terminators do not
have to be used when the Profile is configured with only internal disks or when a
Profile is configured with only external disks. The SCSI termination power for
external terminations at the other end of the SCSI bus is from the +5V supply.
Video Bus Interface
The two Video bus interfaces connect the EDR JPEG Controllers to the Profile
motherboard CCIR 601 serial video crosspoint router. This is through a 96-pin DIN
connector in front of the EISA connector on the motherboard.
PCI Bus Arbitration
Arbitration for the three PCI buses on the EDR, the IB_Bus, the LPCI bus, and the
GPCI bus are all handled by the arbiter/interrupt control PLD, (ARB_INT_PLD). The
arbitration logic is similar for each of the busses and is implemented as a round-robin
scheme which gives equal priority to each master on that bus. However, for
decreasing the latency for the RTP’s access to JPEG controls during time critical
periods, the SCSI chips bus request signals on all LPCI busses are disabled when the
vertical and JPEG interrupts are asserted.