Grass Valley PDR 200 Service Manual - Manual (Page 41)

Master Enhanced Disk Recorder
PDR200 Service Manual 3-9
Real-Time Processor
The Real Time Processor (RTP) consists of an Intel i960HD and RAM executing at a
33Mhz clock rate. It initiates and monitors the following controls:
• JPEG Channels on all EDR boards.
• SCSI Controllers on all EDR boards.
• Fibre Channel network board.
• EISA Direct Memory Access (DMA) channel which is built into the EISA bus
interface for rapidly transfer of data to/from Audio boards.
• Control of other Grass Valley Group supplied EISA boards which implement
Profile capabilities, such as Analog and Serial Digital Video boards, Reference
Generator boards, etc.
• Communication to the system’s application processor.
GPCI Bus Connection
The GPCI bus is an “over-the-top” bus. That is, boards with a GPCI interface must be
placed adjacent to each other in the Profile chassis so that their GPCI edge connectors
are mechanically aligned on the top edge of the boards. The PCI board then plugs
down onto the boards, thereby electrically connecting the GPCI bus to each of them.
The PCI board consists of a small backplane board which routes PCI bus signals,
clocks, interrupts, and arbitration signals from the MEDR board connector. In
addition, the PCI board routes a unique PCI Address/Data line to the identification
select (IDSEL) line on each of the non-master slots. This allows each non-master slot
to be configured using the PCI 2.1 configuration scheme.
RTP to GPCI Interface
The interface from the RTP to the GPCI is through a PCI9060 chip which allows the
RTP to perform direct bus master transfers on the GPCI bus. In addition the chip
provides two independent bi-directional DMA channels with bi-directional FIFOs
supporting burst transfers between RTP memory and memory on other busses
connected to the GPCI.
RTP to EISA Interface
The RTP interfaces to the EISA bus through the following:
• A chip that provides a master interface to an internal PCI bus.
• A high-density programmable logic device that connects that bus to the EISA bus
and provides the master interface to the EISA bus.
• A bi-directional clocked FIFO memory
• Various bus drivers and transceivers.
The master interface and logic device allow the RTP to do single word (4 byte), half
word (2 byte), and single byte transfers to the EISA bus in either the I/O or memory
address regions. The logic device also provides an interrupt to the system processor
via the EISA IRQ10 interrupt line.