Altera Triple Speed Ethernet MegaCore Function - Manual (Page 8)

1 About This MegaCore Function
2014.06.30
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About This MegaCore Function
The Altera ® Triple-Speed Ethernet MegaCore ® function is a configurable intellectual property (IP) core
that complies with the IEEE 802.3 standard. The IP core was tested and successfully validated by the University
of New Hampshire (UNH) interoperability lab. It combines the features of a 10/100/1000-Mbps Ethernet
media access controller (MAC) and 1000BASE-X/SGMII physical coding sublayer (PCS) with an optional
physical medium attachment (PMA).
Device Family Support
For new additions and enhancements to the latest Quartus II software and Altera IP, refer to the What’s
New for Altera IP page of the Altera website.
For a list of IP support for all device families, refer to the All Intellectual Property page of the Altera website.
Features
• Complete triple-speed Ethernet IP: 10/100/1000-Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and
embedded PMA.
• Successful validation from the University of New Hampshire (UNH) InterOperability Lab.
• 10/100/1000-Mbps Ethernet MAC features:
• Multiple variations: 10/100/1000-Mbps Ethernet MAC in full duplex, 10/100-Mbps Ethernet MAC
in half duplex, 10/100-Mbps or 1000-Mbps small MAC (resource-efficient variant), and multiport
MAC that supports up to 24 ports.
• Support for basic, VLAN, stacked VLAN, and jumbo Ethernet frames. Also supports control frames
including pause frames.
• Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.
• Optional statistics counters.
ISO
9001:2008
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