Altera Triple Speed Ethernet MegaCore Function - Manual (Page 113)

Triple-Speed Ethernet System with SGMII
Figure 6-3: Triple-Speed Ethernet System with SGMII with Register Initialization Recommendation
10/100/1000 Mbps MAC External PHY
MAC
Register
Space
MDIO Space 0
MDIO Space 1 MDIO
Host
PHY
Register
Space
MDIO
Slave
Avalon ST TX
Avalon ST RX
Avalon MM
Copper/Fiber
Interface
SGMII Interface (1.25 Gbps)
MDIO
1000BASE-X/
SGMII PCS
PCS
Register
Space
Use the following recommended initialization sequences for the example in Figure 6–4 .
1. External PHY Initialization using MDIO
Refer to step 1 in Triple-Speed Ethernet System with MII/GMII or RGMII on page 6-28.
2. PCS Configuration Register Initialization
a. Set Auto Negotiation Link Timer
//Set Link timer to 1.6ms for SGMII
link_timer (address offset 0x12) = 0x0D40
Link_timer (address offset 0x13) = 0x03
b. Configure SGMII
//Enable SGMII Interface and Enable SGMII Auto Negotiation
//SGMII_ENA = 1, USE_SGMII_AN = 1
if_mode = 0x0003
c. Enable Auto Negotiation
//Enable Auto Negotiation
//AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 can be ignore
PCS Control Register = 0x1140
d. PCS Reset
//PCS Software reset is recommended where there any configuration changed
//RESET = 1
Configuration Register Space Altera Corporation
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Triple-Speed Ethernet System with SGMII 6-30
2014.06.30