Altera Triple Speed Ethernet MegaCore Function - Manual (Page 57)

For more information about the MDIO registers, refer to MAC Configuration Register Space on page 6-1.
MDIO Connection
Figure 4-9: MDIO Interface
PHY
Addr
MDIO Frame
Generation and
Decoding
M
D
IO
In
te
rfa
ce mdc
mdio_in
mdio_out
mdio_oen
PHY
Addr
PHY
Management
Registers
MDIO Frame
Generation &
Decoding
mdio
mdc
addr
PHY
Management
Registers
MDIO Frame
Generation &
Decoding
mdio
mdc
addr
Avalon-MM Control
Interface
10/100/1000 Ethernet MAC
MDIO Frame Format
The MDIO master communicates with the slave PHY device using MDIO frames. A complete frame is 64
bits long and consists of 32-bit preamble, 14-bit command, 2-bit bus direction change, and 16-bit data. Each
bit is transferred on the rising edge of the MDIO clock,
mdc .
Table 4-9: MDIO Frame Formats (Read/Write)
Field settings for MDIO transactions.
Command
PRE Type Idle Data
MSB LSB
TA Addr2
MSB LSB
Addr1
MSB LSB
OP
MSB LSB
ST
MSB LSB
Z xxxxxxxxxxxxxxxx Z0 xxxxx xxxxx 10 01 1 ... 1 Read
Z xxxxxxxxxxxxxxxx 10 xxxxx xxxxx 01 01 1 ... 1 Write
Table 4-10: MDIO Frame Field Descriptions
Description Name
Preamble. 32 bits of logical 1 sent prior to every transaction. PRE
Start indication. Standard MDIO (Clause 22): 0b01. ST
Opcode. Defines the transaction type. OP
Altera Corporation Functional Description
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4-21 MDIO Connection
UG-01008
2014.06.30