Altera Triple Speed Ethernet MegaCore Function - Manual (Page 177)

• Additional checks for configurations that contain the PCS function with optional embedded PMA:
• Transmit frames generated by the frame generator are correctly encapsulated.
• Received frames are de-encapsulated before they are forwarded to the frame monitor.
Testbench Configuration
The testbench is configured, by default, to operate in loopback mode. Frames sent through the transmit path
are looped back into the receive path.
Separate data paths can be configured for single-channel MAC with internal FIFO buffers. In this configu-
ration, the MII/GMII Ethernet frame generator is enabled and the testbench control block simulates
independent yet complete receive and transmit datapaths.
You can also customize other aspects of the testbench using the testbench simulation parameters.
The device under test is configured with the following default settings:
• Link speed is set to Gigabit except for configurations that contain Small MAC. For Small MACs, the
default speed is 100 Mbps.
• Five Ethernet frames of payload length 100, 101, 102, 103 and 104 bytes are transmitted to the system-
side interface and looped back on the ethernet-side interface.
• Default settings for the MAC function:
• The
command_config
register is set to 0x0408003B.
• Promiscuous mode is enabled.
• The maximum frame length, register
frm_length,
is configured to 1518.
• For a single-channel MAC with internal FIFO buffers, the transmit FIFO buffer is set to start data
transmission as soon as its level reaches tx_section_full . The receive FIFO buffer is set to begin
forwarding Ethernet frames to the Avalon-ST receive interface when its level reaches
rx_section_full
.
• Default setting for the PCS function:
• The
if_mode
register is set to 0x0000.
• Auto-negotiation between the local PHY and remote link PHY is bypassed.
Test Flow
The testbench performs the following operations upon a simulated power-on reset:
• Initializes the DUT registers.
• Starts transmission. For a single-channel MAC with internal FIFO buffers, clears the FIFOs.
• Ends transmission and checks the following elements to determine that the simulation is successful:
• No Ethernet protocol errors detected.
• Ethernet frames generated and transmitted are received by the frame monitor.
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10-3 Testbench Configuration
UG-01008
2014.06.30