Altera Triple Speed Ethernet MegaCore Function - Manual (Page 179)

b. Run the following command to set up the required libraries, to compile the generated IP Functional
simulation model, and to exercise the simulation model with the provided testbench:
run__tb.tcl
For more information about simulating Altera IP cores, refer to Simulating Altera Designs in volume
3 of the Quartus II Handbook.
Use the simulation models only for simulation and not for synthesis or any other purposes. Using
these models for synthesis creates a nonfunctional design. Note:
Simulation Model Files
Previously, the Triple-Speed Ethernet MegaCore function generates a .vho or
.vo file for VHDL or Verilog HDL IP functional simulation model.
For the new Triple-Speed Ethernet MegaCore function created in Quartus II ACDS 13.0, the simulation
model will be generated using the industrial standard IEEE simulation encryption.
Table 10-2 lists the scripts available for you to compile the simulation model files in a standalone flow.
Table 10-2: Simulation Model Files
Description Directory Name
Contains a ModelSim script msim_setup.tcl to set up and run a
simulation.
<variation_name>_sim/mentor/
Contains a shell script vcs_setup.sh to set up and run a VCS
®
simulation. <variation_name>_sim/synopsys/
vcs
Contains a shell script vcsmx_setup.sh and synopsys_sim.setup to set
up and run a VCS MX simulation.
<variation_name>_sim/synopsys/
vcsmx
Contains a shell script ncsim_setup.sh and other setup files to set up
and run an NCSIM simulation.
<variation_name>_sim/mentor/
cadence
Altera Corporation Testbench
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10-5 Simulation Model Files
UG-01008
2014.06.30