Altera Triple Speed Ethernet MegaCore Function - Manual (Page 5)

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals...................7-20
10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA
Signals........................................................................................................................................7-22
10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded
PMA...........................................................................................................................................7-25
1000BASE-X/SGMII PCS Signals................................................................................................7-34
1000BASE-X/SGMII PCS and PMA Signals..............................................................................7-38
Timing.........................................................................................................................................................7-39
Avalon-ST Receive Interface........................................................................................................7-39
Avalon-ST Transmit Interface.....................................................................................................7-41
GMII Transmit...............................................................................................................................7-41
GMII Receive..................................................................................................................................7-41
RGMII Transmit............................................................................................................................7-42
RGMII Receive...............................................................................................................................7-42
MII Transmit..................................................................................................................................7-43
MII Receive.....................................................................................................................................7-43
IEEE 1588v2 Timestamp...............................................................................................................7-43
Design Considerations........................................................................................8-1
Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA.............................8-1
MAC and PCS With GX Transceivers..........................................................................................8-2
MAC and PCS With LVDS Soft-CDR I/O...................................................................................8-4
Sharing PLLs in Devices with LVDS Soft-CDR I/O................................................................................8-6
Sharing PLLs in Devices with GIGE PHY................................................................................................8-6
Sharing Transceiver Quads.........................................................................................................................8-7
Migrating From Old to New User Interface For Existing Designs.......................................................8-7
Exposed Ports in the New User Interface.....................................................................................8-7
Timing Constraints.............................................................................................9-1
Creating Clock Constraints........................................................................................................................9-1
Recommended Clock Frequency...............................................................................................................9-3
Testbench...........................................................................................................10-1
Triple-Speed Ethernet Testbench Architecture ....................................................................................10-1
Testbench Components............................................................................................................................10-1
Testbench Verification..............................................................................................................................10-2
Testbench Configuration..........................................................................................................................10-3
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TOC-5 Triple-Speed Ethernet MegaCore Function User Guide