Altera Triple Speed Ethernet MegaCore Function - Manual (Page 39)

Figure 4-2: Multiport MAC Without Internal FIFO Buffers
Configuration and
Statistics
CRC Check
Pause Frame
Termination
Port 0
Loopback
Receiver Control
Transmitter Control
Magic Packet
Detection
CRC Generation
Pause Frame
Generation
Port n
..
.
MDIO Master Configuration and
Statistics
CRC Check
Pause Frame
Termination
Loopback
Receiver Control
Transmitter Control
Magic Packet
Detection
CRC Generation
Pause Frame
Generation
Shared
Configuration
Multiport MAC (Without Internal FIFO Buffers) Ethernet Side
(MII/GMII/RGMII) System Side
(Avalon-ST)
Transmit / Receive
Interfaces
Transmit / Receive
Interfaces
To/From
External PHY
To/From
External PHY
Avalon-MM Interface
In a multiport MAC, the instances share the MDIO master and some configuration registers. You can use
the Avalon-ST Multi-Channel Shared Memory FIFO core in Qsys to store the transmit and receive data.
Related Information
MAC Configuration Register Space on page 6-1
MAC Interfaces
The MAC function implements the following interfaces:
Altera Corporation Functional Description
Send Feedback
4-3 MAC Interfaces
UG-01008
2014.06.30