Altera Triple Speed Ethernet MegaCore Function - Manual (Page 31)

Description Value Name
Determines the Ethernet-side interface of the
MAC block.
• MII—The only option available for 10/100
Mb Small MAC core variations.
• GMII—Available only for 1000 Mb Small
MAC core variations.
• RGMII—Available for 10/100/1000 Mb
Ethernet MAC and 1000 Mb Small MAC core
variations.
• MII/GMII—Available only for 10/100/1000
Mb Ethernet MAC core variations. If this is
selected, media independent interface (MII)
is used for the 10/100 interface, and gigabit
media independent interface (GMII) for the
gigabit interface.
• MII
• GMII
• RGMII
• MII/GMII Interface
Turn on this option to include internal FIFO
buffers in the core. You can only include internal
FIFO buffers in single-port MACs. On/Off Use internal FIFO
Specifies the number of Ethernet ports supported
by the IP core. This parameter is enabled if the
parameter Use internal FIFO is turned off. A
multiport MAC does not support internal FIFO
buffers. 1, 4, 8, 12, 16, 20, and 24 Number of ports
This option is only available for variations that
include the PCS block.
• None—the PCS block does not include an
integrated transceiver module. The PCS block
implements a ten-bit interface (TBI) to an
external SERDES chip.
• LVDS I/O or GXB—the MegaCore function
includes an integrated transceiver module to
implement a 1.25 Gbps transceiver.
Respective GXB module is included for target
devices with GX transceivers. For target
devices with LVDS I/O including Soft-CDR
such as Stratix III, the ALTLVDS module is
included.
• None
• LVDS I/O
• GXB Transceiver type
Ethernet MAC Options
These options are enabled when your variation includes the MAC function. In small MACs, only the following
options are available:
Parameter Settings Altera Corporation
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Ethernet MAC Options 3-2
2014.06.30