Altera Triple Speed Ethernet MegaCore Function - Manual (Page 138)

reconfig_clk
, and
reconfig_busy
—are not present in variations targeting Stratix V devices with GX
transceivers.
1.25 Gbps Serial Interface
If the variant includes an embedded PMA, the PMA provides a 1.25-GHz serial interface.
Table 7-25: 1.25 Gbps MDI Interface Signals
Description I/O Name
125 MHz local reference clock oscillator. I
ref_clk
Serial Differential Receive Interface. I rx_p
Serial Differential Transmit Interface. O
tx_p
Transceiver Native PHY Signal
Table 7-26: Transceiver Native PHY Signal
Description I/O Name
Port to connect the RX PLL reference clock with a frequency of 125
MHz when you enable SyncE support. I
cdr_ref_clk_n
SERDES Control Signals
These signals apply only to PMA blocks implemented in devices with GX transceivers.
Table 7-27: SERDES Control Signal
Description I/O Name
Recovered clock from the PMA block. O rx_recovclkout
Power-down status. Asserted when the PCS function is in power-
down mode; deasserted when the PCS function is operating in normal
mode. This signal is implemented only when an internal SERDES is
used with the option to export the power-down signal.
This signal is not present in PMA blocks implemented in Stratix V
devices with GX transceivers.
O
pcs_pwrdn_out
Power-down enable. Assert this signal to power down the transceiver
quad block. This signal is implemented only when an internal
SERDES is used with the option to export the power-down signal.
This signal is not present in PMA blocks implemented in Stratix V
devices with GX transceivers.
I
gxb_pwrdn_in
Calibration block clock for the ALT2GXB module (SERDES). This
clock is typically tied to the 125 MHz
ref_clk . Only implemented
when an internal SERDES is used.
This signal is not present in PMA blocks implemented in Stratix V
devices with GX transceivers.
I gxb_cal_blk_clk
Altera Corporation Interface Signals
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7-23 1.25 Gbps Serial Interface
UG-01008
2014.06.30