Altera Triple Speed Ethernet MegaCore Function - Manual (Page 26)

4. In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include
in the project. (1) Click Next.
5. In the New Project Wizard: Family & Device Settings page, select the device family and specific device
you want to target for compilation. Click Next.
6. In the EDA Tool Settings page, select the EDA tools you want to use with the Quartus II software to
develop your project.
7. The last page in the New Project Wizard window shows the summary of your chosen settings. Click
Finish to complete the Quartus II project creation.
Specifying IP Core Parameters and Options
Follow these steps to specify IP core parameters and options.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.
The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in
your project. If prompted, also specify the target Altera device family and output file HDL preference.
Click OK.
3. Specify parameters and options for your IP variation:
• Optionally select preset parameter values. Presets specify all initial parameter values for specific
applications (where provided).
• Specify parameters defining the IP core functionality, port configurations, and device-specific features.
• Specify options for generation of a timing netlist, simulation model, testbench, or example design
(where applicable).
• Specify options for processing the IP core files in other EDA tools.
4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation
specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files
for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design
for hardware testing.
5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench
System is not available for some IP cores that do not provide a simulation testbench.
6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example.
Generate > HDL Example is not available for some IP cores.
The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in
Project to manually add a
.qip or .qsys file to a project. Make appropriate pin assignments to connect ports.
Generating a Design Example or Simulation Model
After you have parameterized the MegaCore function, you can also generate a design example, in addition
to generating the MegaCore component files.
In the parameter editor, click Example Design to create a functional simulation model (design example that
includes a testbench). The testbench and the automated script are located in the <variation name>_testbench
directory.
(1) To include existing files, you must specify the directory path to where you installed the MegaCore function.
You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where
you installed the Quartus II software.
Altera Corporation Getting Started with Altera IP Cores
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2-7 Specifying IP Core Parameters and Options
UG-01008
2014.06.30