Altera Triple Speed Ethernet MegaCore Function - Manual (Page 108)

Description R/W Name Bit(s)
Acknowledge. A value of 1 indicates that the link
partner has received 3 consecutive matching ability
values from the device. RO
ACK
14
Copper link partner status:
• 1: copper interface link is up
• 0: copper interface link is down
RO COPPER_LINK_STATUS 15
SGMII PHY Mode Auto Negotiation
When the SGMII mode and the SGMII PHY mode auto-negotiation is enabled, set the
dev_ability
register
before the auto-negotiation process so that the link partner can identify the copper speed, duplex status, and
link status.
When the auto-negotiation is complete, Triple-Speed Ethernet IP core speed and the duplex mode will be
resolved based on the value that you set in the
dev_ability register. You can get the value for the
dev_ability
register from the system level where the Triple-Speed Ethernet IP core is integrated. If the IP
core is integrated in the system level with another IP that resolves the copper speed and duplex information,
use these values to set the
dev_ability
register.
Table 6-17: Dev_Ability Register Bits Description in SGMII PHY Mode
Description R/W Name Bit(s)
Always set bit 0 to 1 and bits1–9 to 0. — Reserved 9:0
Link partner interface speed:
• 00: copper interface speed is 10 Mbps
• 01: copper interface speed is 100 Mbps
• 10: copper interface speed is 1 gigabit
• 11: reserved
RW
SPEED[1:0]
11:10
Link partner duplex capability:
• 1: copper interface is capable of operating in full-
duplex mode
• 0: copper interface is capable of operating in half-
duplex mode
• 1 Gbps speed does not support half-duplex
mode.
RW
COPPER_DUPLEX_STATUS
12
Always set this bit to 0. — Reserved 13
Acknowledge. Value as specified in the IEEE 802.3z
standard. RO
ACK
14
Copper link partner status:
• 1: copper interface link is up
• 0: copper interface link is down
RW
COPPER_LINK_STATUS
15
Altera Corporation Configuration Register Space
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6-25 SGMII PHY Mode Auto Negotiation
UG-01008
2014.06.30