1000base-x/sgmii pcs architecture, 1000base-x/sgmii pcs architecture -25 – Altera Triple Speed Ethernet MegaCore Function User Manual
Page 61

You can configure the PCS function to include an embedded physical medium attachment (PMA) with a a
serial transceiver or LVDS I/O and soft CDR. The PMA interoperates with an external physical medium
dependent (PMD) device, which drives the external copper or fiber network. The interconnect between
Altera and PMD devices can be TBI or 1.25 Gbps serial.
The PCS function supports the following external PHYs:
• 1000 BASE-X PHYs as is.
• 10BASE-T, 100BASE-T and 1000BASE-T PHYs if the PHYs support SGMII.
1000BASE-X/SGMII PCS Architecture
Figure 4-14: 1000BASE-X/SGMII PCS
SGMII
Receive
Converter
SGMII
Transmit
Converter
Configuration
Encapsulation
De -encapsulation
&
Synchronization
Auto-Negotiation
1000BASE -X/SGMII PCS
TBI
Receive
TBI
Transmit
Status
LEDs
Avalon -MM Interface
MII/GMII
Receive
MII/GMII
Transmit
Ethernet Side
MAC Side
8b/10b
Decoder
8b/10b
Encoder
1000 Base-X PCS Receive Control
1000 Base-X PCS Transmit Control
Altera Corporation
Functional Description
4-25
1000BASE-X/SGMII PCS Architecture
UG-01008
2014.06.30
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
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- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)