Altera Triple Speed Ethernet MegaCore Function - Manual (Page 141)

Table 7-28: References
Section Interface Signal
Clock and Reset Signal on page 7-2 Clock and reset signals
MAC Control Interface Signals on page 7-3 MAC control interface
MAC Transmit Interface Signals on page 7-6 MAC transmit interface
MAC Receive Interface Signals on page 7-4 MAC receive interface
Multiport MAC Packet Classification Signals on page 7-14 MAC packet classification signals
Multiport MAC FIFO Status Signals on page 7-15 MAC FIFO status signals
Pause and Magic Packet Signals on page 7-8 Pause and magic packet signals
PHY Management Signals on page 7-10 PHY management signals
1.25 Gbps Serial Interface on page 7-23 1.25 Gbps Serial Signals
Status LED Control Signals on page 7-17 Status LED signals
SERDES Control Signals on page 7-17 SERDES control signals
Transceiver Native PHY Signal on page 7-23 Transceiver Native PHY signal
IEEE 1588v2 RX Timestamp Signals on page 7-26 IEEE 1588v2 RX Timestamp Signals
IEEE 1588v2 TX Timestamp Signals on page 7-27 IEEE 1588v2 TX Timestamp Signals
IEEE 1588v2 TX Timestamp Request Signals on page 7-29 IEEE 1588v2 TX Timestamp Request
Signals
IEEE 1588v2 TX Insert Control Timestamp Signals on page
7-29
IEEE 1588v2 TX Insert Control
Timestamp Signals
IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals on
page 7-32
IEEE 1588v2 ToD Clock Interface Signals
IEEE 1588v2 RX Timestamp Signals
Table 7-29: IEEE 1588v2 RX Timestamp Interface Signals
Description Width I/O Signal
Carries the ingress timestamp on the
receive datapath. Consists of 48-bit seconds
field, 32-bit nanoseconds field, and 16-bit
fractional nanoseconds field.
The MAC presents the timestamp for all
receive frames and asserts this signal in the
same clock cycle it asserts
rx_ingress_
timestamp_96b_valid .
96 O
rx_ingress_timestamp_96b_data_n
Interface Signals Altera Corporation
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IEEE 1588v2 RX Timestamp Signals 7-26
2014.06.30