Altera Triple Speed Ethernet MegaCore Function - Manual (Page 145)

Description Width I/O Signal
Timestamp format of the frame, which the
timestamp inserts.
0: 1588v2 format (48-bits second field + 32-
bits nanosecond field + 16-bits correction
field for fractional nanosecond)
Required offset location of timestamp and
correction field.
1: 1588v1 format (32-bits second field + 32-
bits nanosecond field)
Required offset location of timestamp.
Assert this signal in the same clock cycle as
the start of packet (
avalon_st_tx_
startofpacket is asserted).
1 I
tx_etstamp_ins_ctrl_timestamp_
format
Assert this signal to add residence time
(egress timestamp –ingress timestamp) into
correction field of PTP frame.
Required offset location of correction field.
Assert this signal in the same clock cycle as
the start of packet (
avalon_st_tx_
startofpacket
is asserted).
1 I
tx_etstamp_ins_ctrl_residence_
time_update
96-bit format of ingress timestamp.
(48 bits second + 32 bits nanosecond + 16
bits fractional nanosecond).
Assert this signal in the same clock cycle as
the start of packet (
avalon_st_tx_
startofpacket is asserted).
96 I
tx_etstamp_ins_ctrl_ingress_
timestamp_96b[]
64-bit format of ingress timestamp.
(48-bits nanosecond + 16-bits fractional
nanosecond).
Assert this signal in the same clock cycle as
the start of packet (
avalon_st_tx_
startofpacket is asserted).
64 I
tx_etstamp_ins_ ctrl_ingress_
timestamp_64b[]
Interface Signals Altera Corporation
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UG-01008
IEEE 1588v2 TX Insert Control Timestamp Signals 7-30
2014.06.30