Altera Triple Speed Ethernet MegaCore Function - Manual (Page 197)

Default Description Parameter
1 Sets the
PAD_EN
bit in the
command_config
register. See
Command_Config Register (Dword Offset 0x02) on
page 6-7.
TB_MACPADEN
1518 Maximum frame length.
TB_MACLENMAX
12 Sets the tx_ipg_length register. See Base Configuration
Registers (Dword Offset 0x00 – 0x17) on page 6-3.
TB_IPG_LENGTH
0 Sets the mdio_addr0 register. See Base Configuration
Registers (Dword Offset 0x00 – 0x17) on page 6-3.
TB_MDIO_ADDR0
1 Sets the
mdio_addr1
register. See Base Configuration
Registers (Dword Offset 0x00 – 0x17) on page 6-3.
TB_MDIO_ADDR1
8 Sets the
tx_almost_empty
register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
TX_FIFO_AE
10 Sets the
tx_almost_full
register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
TX_FIFO_AF
8 Sets the rx_almost_empty register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
RX_FIFO_AE
8 Sets the rx_almost_full register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
RX_FIFO_AF
16 Sets the
tx_section_empty
register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
TX_FIFO_SECTION_EMPTY
16 Sets the
tx_section_full
register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
TX_FIFO_SECTION_FULL
0 Sets the
rx_section_empty
register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
RX_FIFO_SECTION_EMPTY
16 Sets the rx_section_full register. See Base
Configuration Registers (Dword Offset 0x00 – 0x17)
on page 6-3.
RX_FIFO_SECTION_FULL
9 Specifies the first n addresses from MCAST_ADDRESSLIST
from which multicast address is selected.
MCAST_TABLEN
Simulation Parameters Altera Corporation
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UG-01008
Functionality Configuration Parameters B-2
2014.06.30