E. packet classifier, Packet classifier block, Packet classifier – Altera Triple Speed Ethernet MegaCore Function User Manual
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E
Packet Classifier
2014.06.30
UG-01008
The Packet Classifier decodes the packet types of incoming PTP packets and returns the decoded information
aligned with SOP to the Triple-Speed Ethernet MAC with IEEE 1588v2 feature.
Packet Classifier Block
Figure E-1: Packet Classifier Block Diagram
Packet Classifier
Avalon-ST DataIn
(Sink)
Ingress Control
Input Signals
Ingress Control
Output Signals
Avalon-ST DataOut
(Source)
Control Signals to
Inserter
Timestamp Field
Location
Data Pipeline
FIFO Packets
FIFO Insert
Control
FIFO Request
Control
Decoding
The components:
• Data Pipeline—holds the data frame up to a specified number of cycles. The number of cycles is determined
by the largest length type field.
• FIFO Packets—holds the Avalon-ST frame data.
• FIFO Insert Control—the ingress control input bus that includes the signals required for decoding logics
and signals to the MAC that is required to be aligned with SOP.
• FIFO Request Control—contains decoded data such as control signals to inserter and timestamp field
locations.
• Decoding—Decodes packet types of incoming PTP packets and returns the decoded data to be stored in
the FIFO request control block.
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