Altera Triple Speed Ethernet MegaCore Function User Manual
Page 191

Description
Value
Constant
Configures the
ENA_10
bit.
25
ALTERA_TSEMAC_CMD_ENA_10_OFST
0x2000000
ALTERA_TSEMAC_CMD_ENA_10_MSK
Configures the
RX_ERR_DISC
bit.
26
ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST
0x4000000
ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK
Configures the
CNT_RESET
bit.
31
ALTERA_TSEMAC_CMD_CNT_RESET_OFST
0x80000000
ALTERA_TSEMAC_CMD_CNT_RESET_MSK
Tx_Cmd_Stat Register (
Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
on page
6-13)
Configures the
OMIT_CRC
bit.
17
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST
0x20000
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK
Configures the
TX_SHIFT16
bit.
18
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST
0x40000
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK
Rx_Cmd_Stat Register (
Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
on page
6-13)
Configures the
RX_SHIFT16
bit
25
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST
0x2000000
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK
Software Programming Interface
Altera Corporation
UG-01008
Constants
11-12
2014.06.30
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)