Ip payload re-alignment, Address insertion, Frame payload padding – Altera Triple Speed Ethernet MegaCore Function User Manual
Page 41: Crc-32 generation
CRC-32 field, and inserts interpacket gap (IPG) bytes. In half-duplex mode, the MAC function also detects
collision and attempts to retransmit frames when a collision occurs. The following conditions trigger
transmission:
• In MAC variations with internal FIFO buffers:
• Cut-through mode—transmission starts when the level of the FIFO level hits the transmit section-full
threshold.
• Store and forward mode—transmission starts when a full packet is received.
• In MAC variations without internal FIFO buffers, transmission starts as soon as data is available on the
Avalon-ST transmit interface.
Related Information
on page 12-1
IP Payload Re-alignment
If you turn the Align packet headers to 32-bit boundaries option, the MAC function removes the additional
two bytes from the beginning of Ethernet frames.
Related Information
on page 4-11
Address Insertion
By default, the MAC function retains the source address received from the user application. You can configure
the MAC function to replace the source address with the primary MAC address or any of the supplementary
addresses by setting the
TX_ADDR_INS
bit in the
command_config
register to 1. The
TX_ADDR_SEL
bits in the
command_config
register determines the address selection.
Related Information
Command_Config Register (Dword Offset 0x02)
on page 6-7
Frame Payload Padding
The MAC function inserts padding bytes (
0x00
) when the payload length does not meet the minimum length
required:
• 46 bytes for basic frames
• 42 bytes for VLAN tagged frames
• 38 bytes for stacked VLAN tagged frames
CRC-32 Generation
To turn on CRC-32 generation, you must set the
OMIT_CRC
bit in the
tx_cmd_stat
register to 0 and send
the frame to the MAC function with the
ff_tx_crc_fwd
signal deasserted.
The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:
FCS(X) = X
32
+X
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
+X
8
+X
7
+X
5
+X
4
+X
2
+X
1
+1
The 32-bit CRC value occupies the FCS field with
X
31 in the least significant bit of the first byte. The CRC
bits are thus transmitted in the following order:
X
31,
X
30,...,
X
1,
X
0.
Altera Corporation
Functional Description
4-5
IP Payload Re-alignment
UG-01008
2014.06.30