Altera Triple Speed Ethernet MegaCore Function - Manual (Page 105)

Description R/W Name Bit(s)
Self-clearing reset bit. Set this bit to 1 to generate a
synchronous reset pulse which resets all the PCS function
state machines, comma detection function, and 8b/10b
encoder and decoder. For normal operation, set this bit to
0 (asynchronous reset value). RW
RESET
15
Status Register (Word Offset 0x01)
Table 6-14: Status Register Bit Descriptions
Description R/W Name Bit
A value of 1 indicates that the PCS function
supports extended registers. RO EXTENDED_CAPABILITY 0
Unused. Always set to 0. —
JABBER_DETECT
1
A value of 1 indicates that a valid link is established.
A value of 0 indicates an invalid link.
If the link synchronization is lost, a 0 is latched.
RO LINK_STATUS 2
A value of 1 indicates that the PCS function
supports auto-negotiation. RO
AUTO_NEGOTIATION_
ABILITY
3
Unused. Always set to 0. — REMOTE_FAULT 4
A value of 1 indicates the following status:
• The auto-negotiation process is completed.
• The auto-negotiation control registers are valid.
RO
AUTO_NEGOTIATION_
COMPLETE
5
Unused. Always set to 0. —
MF_PREAMBLE_SUPPRESSION
6
A value of 1 indicates that the PCS is able to
transmit from MII/GMII regardless of whether the
PCS has established a valid link. RO
UNIDIRECTIONAL_ABILITY
7
Unused. Always set to 0. —
EXTENDED_STATUS
8
Configuration Register Space Altera Corporation
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UG-01008
Status Register (Word Offset 0x01) 6-22
2014.06.30