Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 74)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
74 of 158
ACCUMULATOR (A or ACC)
7 6 5 4 3 2 1 0
SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
ACC.7-0
Bits 7-0 Accumulator. This register serves as the accumulator for arithmetic operations.
It is functionally identical to the accumulator found in the 80C32.
CAN 1 CONTROL REGISTER (C1C)
7 6 5 4 3 2 1 0
SFR E3h ERIE STIE PDE — CRST AUTOB ERCS SWINT
RW-0 RW-0 RW-0 RW-0 RT-1 RW-0 RW-0 RW-1
R = Unrestricted Read, W = Unrestricted Write, T = Timed Access Write Only, -n = Value after Reset
ERIE
Bit 7 CAN 1 Error Interrupt Enable.
0 = CAN 1 Error Interrupt is disabled.
1 = Setting this bit while the C1IE bit (EIE.5) and Global Interrupt Enable bits
(IE.7) are set will generate an interrupt if the CAN 1 Bus Off (BUSOFF) or CAN
1 Error Count Exceeded bit (CECE) bits are set.
STIE
Bit 6 CAN 1 Status Interrupt Enable.
0 = CAN 1 Status Interrupt is disabled.
1 = If the C1IE bit (EIE.5) is set, an interrupt will be generated if the CAN 1
Transmit Status bit (TXS), Receive Status bit (RXS) or the Wake-Up Status bit
(WKS) is set. An interrupt will also be generated if the Status Error bits (ER2-0)
change a non-000b or non-111b state.
PDE
Bit 5 CAN 1 Power-Down Enable. Setting this bit places the CAN 1 module into its
lowest power mode. The module will enter power-down mode immediately upon
setting this bit, or following the completion of the current reception, transmission,
arbitration failure, or error condition on CAN 1. Software can poll the PDE bit to
ascertain whether the microcontroller has entered power-down mode (PDE=1) or
is waiting for a current CAN operation to complete (PDE=0) before entering
power-down Mode.
Power-down mode is exited by clearing the PDE bit or by any reset of the
microcontroller. The CAN 1 module will begin operation after the receipt of 11
consecutive recessive bits.
Reserved
Bit 4 This bit is reserved and must always remain 0. Attempts to set the bit to 1 will
cause improper device operation.