Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 114)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILS
The DS80C390 supports one of three different address modes, selected by the AM1 and AM0 bits in the
ACON register. The processor operates in either the traditional 16-bit address mode, 22-bit paged address
mode or in a 22-bit contiguous address mode. When operating in the 16-bit addressing mode (AM1, AM0
= 00b), all instruction cycle timing and byte counts will be identical to the 8051 family. Use of the 24-bit
paged address mode is binary code-compliant with the traditional (16-bit) 8051 compilers, but allows for
up to 4M bytes of program and 4M bytes of data memory to be supported by a new Address Page SFR
which supports an internal bank switch mechanism. The 22-bit contiguous mode requires a compiler that
supports contiguous program flow over the entire 22-bit address range by the addition of an operand
and/or cycles to eight basic instructions.
16-BIT (8051 STANDARD) ADDRESSING MODE
This addressing mode is identical to that used by the 8051 family and most members of the high-speed
microcontroller family. The microcontroller defaults to this mode following a reset. This mode can also
be used to run code compiled or assembled for the 22-bit contiguous mode, as long as the following
instructions are not executed
:
MOV DPTR, #data24,
ACALL addr19
AJMP addr19
LCALL addr24
LJMP addr24
These four branch instructions are the only instructions that will cause the compiler to generate additional
operands relative to the 16-bit addressing mode. Note that the number of cycles per instruction may
appear different from other instructions, but this is ignored by most assemblers or compilers and as such
does not pose a problem with the binary output.
By selecting the 24-bit contiguous mode prior using any one of these four branch instructions, it is
possible to run 24-bit contiguous compiled code in the default 16-bit address configuration. Once the
AM0 and AM1 bits are set to the 24-bit contiguous address mode, the instructions seen above will
execute properly. When the 24-bit paged address mode is selected, all instructions complied under the
traditional 16-bit address mode will execute normally at any point in code.
22-BIT PAGED ADDRESSING MODE
The DS80C390 incorporates an internal 8-bit Address Page Register (AP),an 8-bit extended DPTR
Register (DPX), an 8-bit extended DPTR1 Register (DPX1), and an 8-bit MOVX Extended Address
Register as hardware support for 22-bit addressing in the paged address mode (AM1, AM0 = 01b). This
mode has two differences in code execution from the traditional 16-bit mode:
1. The first difference is the additional of one machine cycle when executing the ACALL, LCALL, RET
and RETI instructions as well as when the hardware processes an interrupt. This change should be
transparent to most compilers, as the byte count remains identical for these instructions.
2. The second instruction involves register indirect MOVX instructions such as MOVX @Ri, A or
MOVX A, @Ri. When in this mode, the MXAX register supplies the upper 8-bits of the 22-bit (or
23-bit if CMA=1 or IDM1=) address bits of the MOVX address. The complete address is formed by
concatenating MXAX, P2, and R1 or R0 in this mode. The DPTR-related MOVX instructions do not
utilize the P2 and MXAX register.