Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 115)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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The DS80C390 supports interrupts from any location in the 22-bit address field. When an interrupt
request is acknowledged, the current contents of the 22-bit Program Counter (PC) is pushed onto the
stack, and the page value (00h) and the lower 16-bit address of the interrupt vector is then written to the
PC before the execution of the LCALL. This means that all interrupt vectors are fetched from address
0000xxh, rather than the current page as defined by the AP register. The RETI instruction will pop the
three address bytes from the stack, and will restore these bytes back to the PC at the conclusion of the
interrupt service routine. Interrupt service routines that branch over page boundaries must save the current
contents of AP before altering the AP register, as it is not automatically saved on the stack. This
mechanism will support up to three levels of nesting for interrupts.
One extra machine cycle is required to handle the additional byte associated with the extension to 22-bit
addressing. The storage of the 22-bit address during an interrupt, LCALL, or ACALL instruction also
requires three bytes of stack memory as opposed to the traditional two bytes in the 16-bit address mode.
In this mode, the third byte of the PC (PC[22:16]) is not incremented when the lower 16 bits in the lower
two bytes of the PC (PC[15:0]) rolls over from FFFFh to 0000h. In the 22-bit paged address mode
PC[22:16] functions only as a storage register which is loaded by the Address Page (AP) register
whenever the processor executes either a LJMP, ACALL or LCALL instruction. PC[22:16] is stored and
retrieved from the stack with the lower 16-bit of address in PC[15:0] when stack operation is required.
In paged address mode MOVX instructions which utilize the data pointers (such as MOVX @DPTR, A)
will form the 22-bit data address by concatenating the contents of the currently selected extended DPTR
register (DPX or DPX1) with the contents of the DPTR. The values in the DPX and DPX1 registers are
not affected when the lower 16 bits of the selected DPTR overflows or underflowed.
To maintain compatibility with existing 8051 compilers, the JMP @A+DPTR or the MOVC A,
@A+DPTR instructions are limited to the current 64 KB page as specified by the upper 7 bits of the
current instruction execution address register. The contents of the DPX and DPX1 registers will not affect
the operation of either instruction. Note that this differs slightly from the previous discussion of
instructions that use the data pointer.