beautypg.com

Can media arbitration register 0 (cnma0), Can media arbitration register 1 (cnma1), Can bus timing register 0 (cnbt0) – Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement User Manual

Page 125

background image

High-Speed Microcontroller User’s Guide: DS80C390 Supplement

125 of 158

CnMID0 masks programmed to 1 will force the state of the corresponding Data
Byte bit and CAN Media Byte Arbitration Registers 1 and 0 to match before
considering the incoming message a match. Programming either Media ID Mask
Register to 00h effectively disables the Media ID test for that byte. As such the
CnMID1, CnMID0 masks act as a don’t care following a system Reset.


CAN Media Arbitration Register 0 (CnMA0)

MOVX

Address

1

7 6 5 4 3 2 1 0

xxxx01h


CAN Media Arbitration Register 1 (CnMA1)

MOVX

Address

1

7 6 5 4 3 2 1 0

xxxx03h

CAN Media Arbitration Register 1-0. These registers function as the arbitration
field when performing the Media Identification test. If MDME=0, the Media
Identification test will not be performed and the contents of these registers is
ignored. If MDME=1, the CAN module will perform an additional qualifying test
on Data Bytes 0 and 1 of the incoming message, as mentioned in the description of
the CAN Media ID Mask Registers. This register can only be modified during a
software initialization (SWINT=1).


CAN Bus Timing Register 0 (CnBT0)

MOVX

Address

1

7 6 5 4 3 2 1 0

xxxx04h

SJW1 SJW0 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

SJW1, SJW0
Bits 7-6

CAN Synchronization Jump Width Select. These bits specify the maximum
number of time quanta (t

qu

) cycles that a bit may be lengthened or shortened in

one resynchronization to compensate for Phase Errors detected by the CAN
controller when receiving data. These bits can only be modified during a software
initialization (SWINT=1).

SJW1 SJW0 Synchronization Jump Width

(Number in parenthesis is SJW value used in bit timing calculations)

0 0

1

t

qu

(1)

0 1

2

t

qu

(2)

1 0

3

t

qu

(3)

1 1

4

t

qu

(4)

BPR5 - BPR0
Bits 5-0

CAN Baud Rate Prescaler. The sixty four states defined by the binary
combinations of the BPR5 - BPR0 bits determine the value of the prescaler,
which in turn defines the cycle time associated with one time quanta. These bits