Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 101)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
101 of 158
ADDENDUM TO SECTION 8: RESET CONDITIONS
This section supersedes the corresponding section in the High-Speed Microcontroller User’s Guide.
The microprocessor provides several ways to place the CPU in a reset state. It also offers the means for
software to determine the cause of a reset. The reset state of most processor bits is not dependent on the
type of reset, but selected bits do depend on the reset source. The reset sources and the reset state are
described below. The function of the RSTOL pin is also described in this section.
RESET SOURCES
The microprocessor has three ways of entering a reset state, described below. They are:
Power-on/Power Fail Reset
Watchdog Timer Reset
External Reset
POWER-ON/FAIL RESET
The DS80C390 incorporates an internal voltage reference which holds the CPU in the power-on reset
state while V
CC
is below V
RST
. Once V
CC
has risen above V
RST
, the microprocessor will restart the
oscillation of the external crystal and count 65536 clock cycles. This helps the system maintain reliable
operation by only permitting processor operation when voltage is in a known good state. The processor
will then begin software execution at location 0000h.
The processor will exit the reset condition automatically once the above conditions are met. This happens
automatically, needing no external components or action. Execution begins at the standard reset vector
address of 0000h. Software can determine that a Power-on Reset has occurred using the Power-on Reset
flag (POR). It is located at WDCON.6. Since all resets cause a vector to location 0000h, the POR flag
allows software to acknowledge that power failure was the reason for a reset.
Software should clear the POR bit after reading it. When a reset occurs, software will be able to
determine if a power cycle was the cause. In this way, processing may take a different course for each of
the three resets if applicable. When power fails (drops below V
RST
), the power monitor will invoke the
reset state again. This reset condition will remain while power is below the threshold. When power
returns above the reset threshold, a full power-on reset will be performed. Thus a brownout that causes
VCC
to drop below
VRST
appears the same as a power-up.
WATCHDOG TIMER RESET
The Watchdog Timer is a free running timer with a programmable interval. The Watchdog supervises
CPU operation by requiring software to reset it before the time-out expires. If the timer is enabled and
software fails to clear it before this interval expires, the CPU is placed into a reset state. The reset state
will be maintained for two machine cycles. Once the reset is removed, the software will resume execution
at 0000h.
The Watchdog Timer is fully described in Section 11. Software can determine that a Watchdog time-out
was the reason for the reset by using the Watchdog Timer Reset flag (WTRF). WTRF is located at
WDCON.2. Hardware will set this bit to a logic 1 when the Watchdog times out without being cleared by
software if EWT=1. If a Watchdog Timer reset occurs, software should clear this flag manually. This
allows software to detect the event if it occurs again.