Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 152)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
152 of 158
A node is bus off when the transmit error count is greater than or equal to 256. A bus off node will
become error active (no longer bus off) with its error counters both set to 0 after 128 occurrence of 11
consecutive recessive bits have been monitored on the bus.
After exceeding the error passive limit (128), the receive error counter will not be increased any further.
When a message was received correctly, the counter is set again to a value between 119 and 127
(compare with CAN 2.0B specification). After reaching the “bus off“ status, the transmit error counter is
undefined while the receive error counter is cleared and changes its function. The receive error counter
will be incremented after every 11 consecutive recessive bits on the bus. These 11 bits correspond to the
gap between two messages on the bus. If the receive error counter reaches the count 128, following the
bus off recovery sequence, the CAN module changes automatically back to the status of “bus on” and
then sets SWINT = 1. After setting SWINT, all internal flags of the CAN module are reset and the error
counters are cleared. A recovery from a bus off condition does not alter any of the previously
programmed MOVX memory values and will also not alter SFR registers, apart from the transmit and
receive error SFR registers and the error conditions displayed in CAN Status Register. The bus timing
will remain as previously programmed.
BIT TIMING
Bit timing in the CAN 2.0B specification is based on a unit called the nominal bit time. The nominal bit
time is further subdivided into four specific time periods.
1. The SYNC_SEG time segment is where an edge is expected when synchronizing to the CAN Bus.
2. The PROP_SEG time segment is provided to compensate for the physical times associated with
the CAN Bus network
3 & 4. The PHASE_SEG1 and PHASE_SEG2 time segments compensate for edge phase errors. The
PHASE_SEG1 and PHASE_SEG2 time segments can be lengthened or shorted through the use of
the SJW1 and SJW0 bits in the CAN 0/1 Bus Timing Register Zero.
The CAN bus is data is evaluated at the sample point. A time quantum (t
QU
) is a unit of time derived from
the division of the microprocessor crystal oscillator by both the Baud Rate Prescaler (programmed by the
BPR7–BPR0 bits in the COR and CAN 0/1 Bus Timing register) and the System Clock Divider
(programmed by the SCD2 - SCD0 bits in the Clock Output Register). Combining the PROP_SEG and
PHASE_SEG1 time segments into one time period termed t
TSEG1
and equating the SYNC_SEG time
segment to t
SYNC_SEG
and PHASE_SEG2 to t
TSEG2
, provides the basis for the time segments outlined
below and in the CAN Bus Timing SFR Register descriptions. These are shown in the following figure.