Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 38)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
38 of 158
ERCS
Bit 1
CAN 0 Error Count Select. This bit selects the number of transmit or receive
errors that will cause the CAN 0 Error Count Exceeded bit, CECE (C0S.6), to be
set.
0 = CECE bit set when the transmit or receive error counters exceed 9 errors.
1 = CECE bit set when the transmit or receive error counters exceed 127 errors.
SWINT
Bit 0 CAN 0 Software Initialization Enable. This bit enables (SWINT=1) and
disables (SWINT=0) software write access to the first 16 bytes of the CAN 0
MOVX SRAM. These bytes contain the CAN 0 Control/Status/Mask Registers.
Read access to all bytes in the CAN 0 MOVX SRAM is permitted at all times,
regardless of the state of the SWINT bit.
Setting SWINT=1 disables CAN 0 Bus activity, allowing software access to the
CAN 0 Control/Status/Mask Registers without corrupting CAN Bus transmission
or reception. A special lockout procedure delays the internal assertion of the
SWINT bit until all CAN 0 activity has ceased. The following procedure must be
followed when setting the SWINT bit to prevent the accidental corruption of CAN
Bus activity:
1. Write a 1 to the SWINT bit, starting the internal process to enter the
software initialization process.
2. Poll the SWINT bit until it is set. The lockout circuit will hold SWINT=0
if it detects a reception, transmission, or arbitration in progress. When one
of these conditions ceases, or if an error occurs, the CAN module will set
SWINT=1, indicating that the CAN module is disabled and software can
now write to the first 16 bytes of the CAN 0 MOVX SRAM. Attempts to
modify the first 16 bytes of the CAN 0 MOVX SRAM while SWINT=0
will fail, leaving the bytes unchanged.
The SWINT bit controls access to several other bits and registers. The CAN 0
Transmit Error Register (C0TE;A6h) and CAN 0 Receive Error Register
(C0RE;A7h) are only modifiable while SWINT=1.
The BUSOFF bit has a direct interaction with the SWINT bit. When a Bus Off
condition is detected (BUSOFF=1), the CAN module will automatically clear
SWINT=0 and initiate a bus recovery and power-up sequence. Write access to the
SWINT bit is prohibited until the Bus Off condition has been cleared and
BUSOFF has been reset to 0.
The SWINT bit is also set automatically following a system reset, the setting of
the CRST bit in the CAN 0 Control Register, or programming the CAN Bus
Timing Registers (C0BT0, C0BT1 in the MOVX SRAM) to 00h (an invalid
state). As a precaution against utilizing the CAN with invalid bus timing, the
SWINT bit cannot be cleared while C0BT0=C0BT1=00h. When this bit is
cleared, the CAN 0 module will initiate a CAN Bus synchronization after the
CAN module executes a power-up sequence (reception of 11 consecutive
recessive bits.)