Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 21)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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CLOCK CONTROL (CKCON)
7 6 5 4 3 2 1 0
SFR 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
WD1, WD0
Bits 7-6 Watchdog Timer Mode Select 1-0. These bits select the watchdog timer time-
out period, which determines the timing of the watchdog timer interrupt and the
watchdog timer reset.
WD1 WD0 Interrupt time-out Reset time-out
0 0 2 17 system clocks 2 17 + 512 system clocks
0 1 2 20 system clocks 2 20 + 512 system clocks
1 0 2 23 system clocks 2 23 + 512 system clocks
1 1 2 26 system clocks 2 26 + 512 system clocks
The system clock relates to the external clock as follows:
Clock Mode External clocks per system clock
Frequency Multiplier (4x) 0.25
Frequency Multiplier (2x) 0.5
Divide-by-4 1
Power Management Mode 256
T2M
Bit 5 Timer 2 Clock Select. This bit controls the division of the system clock that
drives Timer 2. This bit has no effect when the timer is in baud rate generator or
clock output modes. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 2 uses a divide-by-12 of the system clock frequency.
1 = Timer 2 uses a divide-by-4 of the system clock frequency.
T1M
Bit 4 Timer 1 Clock Select. This bit controls the division of the system clock that
drives Timer 1. Clearing this bit to 0 maintains 80C32 compatibility. This bit has
no effect on instruction cycle timing.
0 = Timer 1 uses a divide-by-12 of the system clock frequency.
1 = Timer 1 uses a divide-by-4 of the system clock frequency.
T0M
Bit 3 Timer 0 Clock Select. This bit controls the division of the system clock that
drives Timer 0. Clearing this bit to 0 maintains 80C32 compatibility. This bit has
no effect on instruction cycle timing.
0 = Timer 0 uses a divide-by-12 of the system clock frequency.
1 = Timer 0 uses a divide-by-4 of the system clock frequency.