Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 102)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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EXTERNAL RESET
If the RST input is taken to a logic 1, the CPU will be forced into a reset state. This will not occur
instantaneously, as the condition must be detected and then clocked into the microprocessor. It requires a
minimum of two machine cycles to detect and invoke the reset state. Thus the reset is a synchronous
operation and the crystal must be running to cause an external reset.
Once the reset state is invoked, it will be maintained as long as RST=1. When the RST is removed, the
CPU will exit the reset state within two machine cycles and begin execution at address 0000h. All
registers will default to their power-on reset state. There is no flag to indicate that an external reset was
applied. However, since the other two sources have associated flags, the RST pin is the default source
when neither POR or WTRF is set.
If a RST is applied while the processor is in the Stop mode, the scenario changes slightly. As mentioned
above, the reset is synchronous and requires a clock to be running. Since the Stop mode stops all clocks,
the RST will first cause the oscillator to begin running and force the program counter to 0000h. Rather
than a two machine cycle delay as described above, the processor will apply the full power-on delay
(65536 clocks) to allow the oscillator to stabilize.
RESET OUTPUTS
The microprocessor has one reset output, the RSTOL pin.
Reset Output Low ( RSTOL )
This external output pin is active low whenever the microprocessor is in a reset state. It can be used to
signal to external devices than an otherwise invisible internal reset is in progress. It will be active under
the following conditions:
When the processor has entered reset by the RST pin
During the crystal warm-up period following a power-on reset or stop mode
During a watchdog timer reset. (
RSTOL will be active for 2 machine cycles)
During an oscillator failure (OFDE=1).
RESET STATE
Regardless of the source of the reset, the state of the microprocessor is the same while in reset. When in
reset, the oscillator is running, but no program execution is allowed. When the reset source is external, the
user must remove the reset stimulus. When power is applied to the device, the power-on delay removes
the stimulus automatically.
Resets do not affect the Scratchpad RAM. Thus any data stored in RAM will be preserved. The contents
of internal MOVX data memory will also remain unaffected by a reset. Note that if the power supply dips
below approximately 2V, the RAM contents may be lost. The minimum voltage required for RAM data
retention in not specified. Since it is impossible to determine if the power was lower than 2V prior to the
power–on reset, RAM must be assumed lost when POR is set.
The reset state of SFR bits are described in Section 4. Bits which are marked SPECIAL have conditions
which can affect their reset state. Consult the individual bit descriptions for more information. Note that
the stack pointer will also be reset. Thus the stack is effectively lost during a reset even though the RAM