Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 113)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
113 of 158
ADDENDUM TO SECTION 13: TIMED ACCESS PROTECTION
A number of timed-access protected bits are associated with the new features of the DS80C390. Please
consult the High-Speed Microcontroller User’s Guide for complete information on the use of the timed-
access feature.
POR (WDCON.6):
Power-on Reset
WDIF (WDCON.3): Watchdog Interrupt Flag
EWT (WDCON.1): Watchdog Timer Enable
RWT (WDCON.0): Watchdog Reset
BGS (EXIF.0): Bandgap Stop
SA (ACON.2): Stack Address Mode
AM1-AM0 (ACON.1-ACON.0): Address Mode Bit 1 and Bit 0
IDM1-IDM0 (MCON.7-MCON.6): Internal Memory Configuration and Location
Bits 1 and 0
CMA (MCON.5): CAN Data Memory Assignment
PDCE3-PDCE.0 (MCON.3-MCON.0) Program/Data Chip Enables
CRST (C0C.3): CAN 0 Reset
CRST (C1C.3): CAN 1 Reset
SBCAN (P4CNT.6): Single Bus CAN
P4CNT.5-P4CNT.0: Port 4 Pin Configuration Control Bits
P5CNT.2-P5CNT.0: Port 5 Pin (P5.7-P5.5) Configuration Control
Bits
IRDACK (COR.7): IRDA Clock Output Enable
C1BPR7-C1BPR6 (COR.6-COR.5): CAN 1 Baud Rate Prescale Bits
C0BPR7-C0BPR6 (COR.4-COR.3): CAN 0 Baud Rate Prescale Bits
COD1-COD0 (COR.2-COR.1): CAN Clock Output Divide Bit 1 and Bit 0
CLKOE (COR.0): CAN Clock Output Enable