Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 104)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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ADDENDUM TO SECTION 10: PARALLEL I/O
Changes to this section primarily involve the additional functionality associated with Port 4 and 5, and
the use of Port 1 as the address LSB in nonmultiplexed memory mode. Because the DS80C390 is a
ROMless device, Port 0 and 2 do not support general-purpose I/O.
PORT 1
General-Purpose I/O
When the device is operating in multiplexed memory mode ( MUX pin is connected to a logic low) port 1
serves as a general purpose I/O port. Data written to the port latch serves to set both level and direction of
the data on the pin. More detail on the functions of port 1 pins configured for general-purpose I/O is
provided under the description of port 1 and port 3 in the High-Speed Microcontroller User’s Guide.
Nonmultiplexed Address Bus A0-A7
When the device is operating in nonmultiplexed memory mode ( MUX pin is connected to a logic high)
port 1 serves LSB of the external address bus. When operating as the LSB of the address bus the port 1
pins have extremely strong drivers that allow the bus to move 100 pF loads with the timing shown in the
electrical specifications.
When used as an address bus, the A0-7 pins will provide true drive capability for both logic levels. No
pullups are needed. In fact, pullups will degrade the memory interface timing. Members of the high-speed
microcontroller family employ a two-state drive system on A0-7. That is, the pin is driven hard for a
period to allow the greatest possible setup or access time. Then the pin states are held in a weak latch
until forced to the next state or overwritten by an external device. This assures a smooth transition
between logic states and also allows a longer hold time. In general, the data is held (hold time) on A0-7
until another device overwrites the bus. This latch effect is generally transparent to the user.
Current-Limited Transitions
The DS80C390 does not employ the current-limited transition feature described in the High-Speed
Microcontroller User’s Guide
.
PORTS 4 AND 5
Ports 4 and 5 are general-purpose I/O ports with optional special functions associated with each pin.
Enabling the special function automatically converts the I/O pin to that function. To insure proper
operation, each alternate function pin should be programmed to a logic 1.
The drive characteristics of these pins may change depending on whether the pin is configured for general
I/O or as the special function associated with that pin. When in I/O mode, the logic 0 is created by a
strong pulldown. The logic 1 is created by a strong transition pullup that changes to a weak pullup. When
a pin is configured in its alternate function, and that function concerns memory interfacing (A16-A17,
3 0 PCE − , or 3 0 CE − ) the pins will be driven using the stronger memory interface values shown in the
DC electrical characteristics of the data sheet.