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Can 0 m, Essage, Enter – Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement User Manual

Page 49: Ontrol, Egister, C0m2c), C0m3c)

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High-Speed Microcontroller User’s Guide: DS80C390 Supplement

49 of 158

after the message center read. If DTUP has been set, then a new
message was received and software should read the message center
again to read the new data. If DTUP remained cleared, no additional
data was received and the data is complete.
If WTOE=0 the processor is not permitted to overwrite this message
center, so it is only necessary to clear the DTUP bit after reading the
message center.

The state of the DTUP bit in the receive mode does not inhibit remote frame
request transmission in the receive mode. The only gating item for remote
frame transmission in the receive mode is that the MSRDY and MTRQ bits
must both be set.

T/ R =1 (transmit)
In this mode, software must set TIH =1 and clear DTUP = 0 prior to doing an
update of the associated message center. This prevents the CAN module from
transmitting the data while the microcontroller is updating it. Once the
microcontroller has finished configuring the message center, software must clear
TIH = 0 and set MSRDY=MTRQ =DTUP =1, to enable the CAN module to
transmit the data.
The CAN module will not clear the DTUP after the transmission, but the
microcontroller can verify that the transmission has been completed, by
checking the MTRQ bit, which will be cleared (MTRQ = 0) after the
transmission has been successfully completed.

CAN 0 MESSAGE CENTER 2 CONTROL REGISTER (C0M2C)

7 6 5 4 3 2 1 0

SFR ACh

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ ROW/TIH

DTUP

RW-0 RW-0 RW-0 RW-0 RC-0 R*-0 R*-0 R*-0

R = Unrestricted Read, C = Clear Only, * = See description below, -n = Value after Reset

C0M2C
Bits 7-0

Operation of the bits in this register are identical to those found in the CAN 0
Message One Control Register (C0M1C;ABh). Please consult the description
of that register for more information.

CAN 0 MESSAGE CENTER 3 CONTROL REGISTER (C0M3C)

7 6 5 4 3 2 1 0

SFR ADh MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ ROW/TIH

DTUP

RW-0 RW-0 RW-0 RW-0 RC-0 R*-0 R*-0 R*-0

R = Unrestricted Read, C = Clear Only, * = See description below, -n = Value after Reset

C0M3C
Bits 7-0

Operation of the bits in this register are identical to those found in the CAN 0
Message One Control Register (C0M1C;ABh). Please consult the description
of that register for more information.