Motorola MVME172 - Manual (Page 40)

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Board Description and Memory Maps
1
Table 1-7. VMEchip2 Memory Map (Sheet 1 of 3)
DMA TB
SNP MODE
ROM
ZERO
SRAM
SPEED
ADDER
2
SLAVE ENDING ADDRESS 1
SLAVE ENDING ADDRESS 2
SLAVE ADDRESS TRANSLATION ADDRESS 1
SLAVE ADDRESS TRANSLATION ADDRESS 2
BLK
D64
SNP
2
WP
2
SUP
2
USR
2
A32
2
A24
2
BLK
2
PRGM
2
DATA
2 2
MASTER ENDING ADDRESS 1
MASTER ENDING ADDRESS 2
MASTER ENDING ADDRESS 3
MASTER ENDING ADDRESS 4
MASTER ADDRESS TRANSLATION ADDRESS 4
VMEchip2 LCSR Base Address = $FFF40000
OFFSET:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MAST
D16
EN
MAST
WP
EN
MAST
D16
EN
MAST
WP
EN
MASTER AM 3 MASTER AM 4
GCSR GROUP SELECT
GCSR
BOARD SELECT
MAST
4
EN
MAST
3
EN
MAST
2
EN
MAST
1
EN
TICK
2/1
TICK
IRQ 1
EN
CLR
IRQ
IRQ
STAT
VMEBUS
INTERRUPT
LEVEL
VMEBUS INTERRUPT VECTOR
0
4
8
C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
WAIT
RMW
DMA CONTROLLER
DMA CONTROLLER
DMA CONTROLLER
DMA CONTROLLER
This sheet continues on facing page.