Motorola MVME172 - Manual (Page 305)

Programming Model
http://www.mcg.mot.com/literature 5-15
5
Memory Configuration Register
MSIZ2-MSIZ0
MSIZ2-MSIZ0 together define the size of the total
memory to be controlled by the MCECC pair. These bits
reflect the RSIZ2-RSIZ0 bits in the Defaults Register 1.
Difference from MEMC040: NONE except that they reflect
input pins on the MEMC040; while they reflect register bits that
are initialized by the reset serial bit stream on the MCECC.
ADR/SIZ 1st $FFF43008/2nd $FFF43108 (8-bits)
BIT 31 30 29 28 27 26 25 24
NAME 0 0 FSTRD RB4 RB3 MSIZ2 MSIZ1 MSIZ0
OPER R R R R R R R R
RESET X X X X X X X X
MSIZ2 MSIZ1 MSIZ0 Memory Size
0 0 0 4MB using one 144-bit wide
block of 256Kx4 DRAMs
0 0 1 8MB using two 144-bit wide
block of 256Kx4 DRAMs
0 1 0 16MB using one 144-bit wide
block of 1Mx4 DRAMs
0 1 1 32MB using two 144-bit wide
blocks of 1Mx4 DRAMs
1 0 0 64MB using one 144-bit wide
block of 4Mx4 DRAMs
1 0 1 128MB using two 144-bit wide
blocks of 4Mx4 DRAMs
1 1 0 Reserved
1 1 1 Reserved