Motorola MVME172 - Manual (Page 209)

Programming Model
http://www.mcg.mot.com/literature 3-21
3
Tick Timer 1 Interrupt Control Register
IL2-IL0 These three bits select the interrupt level for the tick
timers. Level 0 does not generate an interrupt.
ICLR Writing a logic 1 to this bit clears the tick timer interrupt
(i.e., INT bit in this register). This bit is always read as
zero.
IEN When this bit is set high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
INT When this bit is high a Tick Timer interrupt is being
generated at the level programmed in IL2-IL0 (if
nonzero). This bit is edge-sensitive and can be cleared by
writing a logic 1 into the ICLR control bit.
ADR/SIZ $FFF4201B (8 bits)
BIT 7 6 5 4 3 2 1 0
NAME INT IEN ICLR IL2 IL1 IL0
OPER R R R R/W C R/W R/W R/W
RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL