Motorola MVME172 - Manual (Page 344)

Index
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I
N
D
E
X
IP ID space 4-51
setting up interrupt handler routine B-2
setting up local bus interrupter B-2
using bus timers 1-57
extended access cycles 2-34 , 2-37
F
fair mode, VMEchip2 2-8 , 2-14
features
IP2 chip 4-1
MC2 chip 3-1
MCECC 5-1
MVME172 1-3
VMEchip2 2-1
Flash Access Time Control Register 3-40
Flash memory device 1-3
Flash/EPROM interface 3-2
functional blocks, VMEchip2 2-4
functional description
IP2 chip 4-2
MC2 chip 3-2
MCECC 5-2
MVME172 1-5
VMEchip2 2-4
G
GCSR
base address registers, programming
2-37
board address 2-48
group address 2-47
map decoder 1-47
programming model 2-101
SIG3-0 interrupters 2-19
programming 2-103
GCSR, VMEchip2 2-20 , 2-101
General Control Registers, IP2 chip 4-24
general description
IP2 chip 4-2
MCECC 5-2
General Purpose
I/O pins 2-97
Inputs Register 3-33
Readable Jumpers Header 1-5
Register 0 2-108
Register 1 2-108
Register 2 2-109
Register 3 2-109
Register 4 2-110
Register 5 2-110
general purpose registers 2-102
Global Control and Status Registers (GCSR)
2-20 , 2-101
global reset 2-18
global reset driver 2-18
global time-out timer, VMEbus 2-66
GPI inputs, addresses 1-9
GPI3 jumper 1-13 , 3-34
group address, GCSR 2-47
I
I/O
and ID space accesses, IP 4-54
Control Register 1 2-97
Control Register 2 2-98
Control Register 3 2-98
interfaces 1-3
map decoders 2-6 , 2-37 , 2-39
memory maps 1-21
I/O space
32-bit IP_ab 4-50
IP_a 4-49
IACK
cycle 2-19
daisy-chain 2-16
daisy-chain driver 2-17
ID Register
VMEchip2 2-105
ID space, IP 4-51
indivisible cycles, MC68060 1-58