Motorola MVME172 - Manual (Page 347)

http://www.mcg.mot.com/literature IN-7
I
N
D
E
X
MC2 chip/VMEchip2 redundancies 1-5
MC68060
bus master support for 82596CA 3-4
indivisible cycles 1-58
indivisible RMW memory accesses 1-58
MCECC 5-1
features 5-1
functional description 5-2
internal register memory map 5-10
introduction 5-1
specifications 5-3
MCECC chip Memory Controller ASIC 1-3
MCECC internal register memory map
memory map
MCECC internal register 1-35
Memory Base Address Registers, IP2 chip
4-19
Memory Configuration Register 5-15
memory maps
BBRAM configuration area 1-41
BBRAM, TOD clock 1-40
Ethernet LAN 1-38
IP2 chip devices 4-9
IP2 chip, all devices 1-28
IP2 chip, Control and Status Registers
1-29 , 4-11
local bus 1-9
local bus, 200/300-Series 1-10
local bus, 400/500-Series 1-12
local I/O devices, 200/300-Series 1-14
local I/O devices, 400/500-Series 1-18
MC2 chip 1-27
MCECC internal registers 5-10
SCSI 1-39
time-of-day clock 1-42
VMEbus 1-46
VMEchip2 GCSR 1-26 , 2-104
VMEchip2 LCSR 1-22 , 2-22
Z85230 SCC register 1-37
memory map of the MC2 chip registers 3-8
memory mezzanine board serial number 1-45
Memory Size Registers, IP2 chip 4-21
memory space
16-bit IP_a 4-47
32-bit IP_ab 4-48
8-bit IP_a 4-46
memory space accesses, IP 4-52
microprocessor 1-3
MIEN 2-75 , 2-97 , 3-12
Miscellaneous Control Register 2-99
MK48T58 memory map 1-40
MPU
local bus time-out 1-51
off-board error 1-51
parity error 1-50
Status and DMA Interrupt Count
Register 2-63
Status Register 3-46
VMEchip2 and 2-52
MPU TEA, cause unidentified 1-51
MVIP IndustryPack interfaces 1-4
MVME172
features 1-3
functional description 1-5
introduction 1-1
MVME172 Version Register 3-35
MVME712x transition boards 1-2
N
no address increment DMA transfers 2-12
non-ECC DRAM controller 3-5
non-privileged access cycles 2-34 , 2-37
Non-Volatile RAM (NVRAM) 1-3
no-VMEbus option 1-5
NVRAM memory map 1-40
O
overflow counter 2-73 , 2-74
overview, MVME172 1-1
P
P2 chip 1-2
parity checking 3-5
performance, MCECC 5-2