Motorola MVME172 - Manual (Page 304)

5-14 Computer Group Literature Center Web Site
MCECC
5
Chip ID Register
The Chip ID Register is hard-wired to a hexadecimal value of $81. The
MCECC can be given a software reset by writing a value of $0F to this
register. This write is terminated properly with TA*, and sets most internal
registers to their default (power-up) state. Writes of any value other than
$0F to this register are ignored; however, the MCECC always terminates
the cycles properly with TA*.
Difference from MEMC040: value = $80 for MEMC040;
value = $81 for MCECC.
Chip Revision Register
The Chip Revision Register is hard-wired to reflect the revision level of the
MCECC ASIC. The current value of this register is $00. Writes to this
register are ignored; however, the MCECC pair always terminates the
cycles properly with TA*.
Difference from MEMC040: none between corresponding
revisions of the two parts.
ADR/SIZ 1st $FFF43000/2nd $FFF43100 (8-bits)
BIT 31 30 29 28 27 26 25 24
NAME CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0
OPER R R R R R R R R
RESET X X X X X X X X
ADR/SIZ 1st $FFF43004/2nd $FFF43104 (8-bits)
BIT 31 30 29 28 27 26 25 24
NAME REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
OPER R R R R R R R R
RESET X X X X X X X X