Motorola MVME172 User Manual

Motorola Hardware

MVME172

VME Embedded Controller

Programmer’s

Reference Guide

VME172A/PG2

Edition of February 1999

Table of contents

Document Outline

Contents
- FIGURES
- TABLES
Board Description and Memory Maps
Introduction
Overview
Requirements
Block Diagrams
Functional Description
- No-VMEbus-Interface Option
- VMEbus Interface and VMEchip2
Memory Maps
- Local Bus Memory Map
- VMEbus Memory Map
  - VMEbus Accesses to the Local Bus
  - VMEbus Short I/O Memory Map
Software Support Considerations
- Interrupts
- Cache Coherency
- Sources of Local BERR*
- Description of Error Conditions on the MVME172
- Example of the Proper Use of Bus Timers
- MVME172 MC68060 Indivisible Cycles
- Illegal Access to IP Modules from External VMEbus Masters
VMEchip2
Introduction
- Summary of Major Features
Functional Blocks
- Local Bus to VMEbus Interface
  - Local Bus to VMEbus Requester
- VMEbus to Local Bus Interface
- Local Bus to VMEbus DMA Controller
  - No Address Increment DMA Transfers
  - DMAC VMEbus Requester
- Tick and Watchdog Timers
- VMEbus Interrupter
- VMEbus System Controller
- Local Bus Interrupter and Interrupt Handler
- Global Control and Status Registers
LCSR Programming Model
- Programming the VMEbus Slave Map Decoders
- Programming the Local Bus to VMEbus Map Decoders
- Programming the VMEchip2 DMA Controller
- Programming the Tick and Watchdog Timers
- Programming the Local Bus Interrupter
GCSR Programming Model
- Programming the GCSR
MC2 Chip
Introduction
- Summary of Major Features
Functional Description
- MC2 Chip Initialization
- Flash and PROM Interface
- BBRAM Interface
- 82596CA LAN Interface
- 53C710 SCSI Controller Interface
- SRAM Memory Controller
- NON-ECC DRAM Memory Controller
- Z85230 SCC Interface
- Tick Timers
- Watchdog Timer
- Local Bus Timer
Memory Map of the MC2 Chip Registers
Programming Model
- MC2 Chip ID Register
- MC2 Chip Revision Register
- General Control Register
- Interrupt Vector Base Register
- Programming the Tick Timers
  - Tick Timer 1 and 2 Compare and Counter Registers
  - LSB Prescaler Count Register
  - Prescaler Clock Adjust Register
  - Tick Timer 1 and 2 Control Registers
  - Tick Timer Interrupt Control Registers
- DRAM Parity Error Interrupt Control Register
- SCC Interrupt Control Register
- Tick Timer 3 and 4 Control Registers
- DRAM and SRAM Memory Controller Registers
  - DRAM Space Base Address Register
  - SRAM Space Base Address Register
  - DRAM Space Size Register
  - DRAM/SRAM Options Register
  - SRAM Space Size Register
- LANC Error Status Register
- 82596CA LANC Interrupt Control Register
- LANC Bus Error Interrupt Control Register
- SCSI Error Status Register
- General Purpose Inputs Register
- MVME172 Version Register
- SCSI Interrupt Control Register
- Tick Timer 3 and 4 Compare and Counter Registers
- Bus Clock Register
- PROM Access Time Control Register
- Flash Access Time Control Register
- ABORT Switch Interrupt Control Register
- RESET Switch Control Register
- Watchdog Timer Control Register
- Access and Watchdog Time Base Select Register
- DRAM Control Register
- MPU Status Register
- 32-bit Prescaler Count Register
IP2 Chip
Introduction
- Summary of Major Features
Functional Description
- General Description
- Cache Coherency
- Local Bus to IndustryPack DMA Controllers
- Clocking Environments and Performance
- Programmable Clock
- Error Reporting
- Interrupts
Overall Memory Map
Programming Model
- Chip ID Register
- Chip Revision Register
- Vector Base Register
- IP_a, IP_b, IP_c, IP_d Memory Base Address Registers
- IP_a, IP_b, IP_c, IP_d Memory Size Registers
- IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control Registers
- IP_a, IP_b, IP_c, and IP_d; General Control Registers
- IP Clock Register
- DMA Arbitration Control Register
- IP RESET Register
- Programming the DMA Controllers
Local Bus to IndustryPack Addressing
- 8-Bit Memory Space
- 16-Bit Memory Space
- 32-Bit Memory Space
- IP_a I/O Space
- IP_ab I/O Space
- IP_a ID Space
IP to Local Bus Data Routing
- Memory Space Accesses
- I/O and ID Space Accesses
MCECC
Introduction
Features
Functional Description
- General Description
- Performance
- Cache Coherency
- ECC
- Error Logging
- Scrub
- Refresh
- Arbitration
- Chip Defaults
Programming Model
- Chip ID Register
- Chip Revision Register
- Memory Configuration Register
- Dummy Register 0
- Dummy Register 1
- Base Address Register
- DRAM Control Register
- BCLK Frequency Register
- Data Control Register
- Scrub Control Register
- Scrub Period Register Bits 15-8
- Scrub Period Register Bits 7-0
- Chip Prescaler Counter
- Scrub Time On/Time Off Register
- Scrub Prescaler Counter (Bits 21-16)
- Scrub Prescaler Counter (Bits 15-8)
- Scrub Prescaler Counter (Bits 7-0)
- Scrub Timer Counter (Bits 15-8)
- Scrub Timer Counter (Bits 7-0)
- Scrub Address Counter (Bits 26-24)
- Scrub Address Counter (Bits 23-16)
- Scrub Address Counter (Bits 15-8)
- Scrub Address Counter (Bits 7-4)
- Error Logger Register
- Error Address (Bits 31-24)
- Error Address (Bits 23-16)
- Error Address Bits (15-8)
- Error Address Bits (7-4)
- Error Syndrome Register
- Defaults Register 1
- Defaults Register 2
- Initialization
Syndrome Decode
Related Documentation
Motorola Computer Group Documents
- Literature Updates
Manufacturers’ Documents
Using Interrupts on the MVME172
Introduction
VMEchip2 Tick Timer 1 Periodic Interrupt Example
Index