Motorola MVME172 - Manual (Page 270)

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IP2 Chip
4
DMA Status Register
DONE This bit is set when DMAC has finished executing
commands and there were no errors, or DMAC has
finished executing commands because the DHALT bit
was set. This bit is cleared when DMAC is enabled. A
DMAC interrupt will be generated if interrupts are
enabled.
IPTO When this bit is set, a DMAC access to an IndustryPack
timed out. This bit is cleared when DMA is enabled. A
DMAC interrupt will be generated if interrupts are
enabled.
TBL When this bit is set, DMAC received an error on the local
bus while it was reading commands from the command
packet. Additional information is provided in bit 6
(DLBE). This bit is cleared when DMAC is enabled.
DLBE When this bit is set, DMAC received a TEA. (TEA is
transfer error acknowledge signal on the MC68060 local
bus. It indicates that a time-out occurred.) This bit is
cleared when DMAC is enabled. A DMAC interrupt will
be generated if interrupts are enabled.
CHANI When this bit is set, the INTE bit in the DMA Control
Register 2 was detected. This bit is cleared when DMA is
enabled or the interrupt status bit is cleared in the DMA
interrupt control register or the DHALT bit was detected
in the DMA Control Register 1. A DMAC interrupt will
be generated if interrupts are enabled.
ADR/SIZ $FFFBC020, $38, $50, $68 (8 bits each)
BIT 7 6 5 4 3 2 1 0
NAME 0 DLBE 0 IPEND CHANI TBL IPTO DONE
OPER R R R R R R R R
RESET 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R