Motorola MVME172 - Manual (Page 28)

1-10 Computer Group Literature Center Web Site
Board Description and Memory Maps
1
map from $00000000 to $FFFFFFFF. Many areas of the map are
user-programmable, and suggested uses are shown in the table. The cache
inhibit function is programmable in the MC68xx060 MMU. The onboard
I/O space must be marked cache inhibit and serialized in its page table.
Table 1-3 on page 1-10 further defines the map for the local I/O devices
for the 200/300-Series MVME172, and Table 1-4 on page 1-12 further
defines the map for the local I/O devices for the 400/500-Series
MVME172.
Table 1-3. 200/300-Series MVME172 Local Bus Memory Map
Address Range Devices Accessed
Port
Width
Size
Software
Cache
Inhibit
Notes
Programmable DRAM on parity
mezzanine D32 4MB-16MB N 2
Programmable DRAM on ECC
mezzanine D32 4MB-64MB N 2
Programmable Onboard SRAM D32 128KB N 2
Programmable VMEbus A32/A24 D32-D16 -- ? 4
Programmable IP_a memory D32-D8 64KB-8MB ? 2, 4
Programmable IP_b memory D32-D8 64KB-8MB ? 2, 4
$FF800000-$FF9FFFFF Flash/EPROM D32 2MB N 1, 5
$FFA00000-$FFBFFFFF EPROM/Flash D32 2MB N 5
$FFC00000-$FFDFFFFF Not decoded D32 2MB N
$FFE00000-$FFE1FFFF Onboard
SRAM default D32 128KB N
$FFE80000-$FFEFFFFF Not decoded -- 512KB N 6
$FFF00000-$FFFEFFFF Local I/O devices
(see next table) D32-D8 878KB Y 3
$FFFF0000-$FFFFFFFF VMEbus A16 D32/D16 64KB ? 2, 4