Motorola MVME172 User Manual
Page 343

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IN-3
I
N
D
E
X
DMA continued
Interrupt Control Register, IP2 chip
Local Bus Address Counter, IP2 chip
Status Register, IP2 chip
Table Address Counter, IP2 chip
DMAC
byte counter
command packets
Control Register 1 (bits 0-7)
Control Register 2 (bits 0-7)
Control Register 2 (bits 8-15)
interrupter
local bus address counter
LTO error
off-board error
parity error
Status Register
TEA, cause unidentified
VMEbus address counter
VMEbus error
VMEbus requester
documentation
double bit error (cycle type = burst read or
non-burst read)
double bit error (cycle type = non-burst write)
double bit error (cycle type = scrub)
DRAM
and SRAM Memory Controller
Registers
Control Register
Parity Error Interrupt Control Register
performance
size control bit encoding
Space Base Address Register
DRAM/SRAM Options Register
DTACK
Dummy Register 0
Dummy Register 1
DWB pin
E
ECC
edge-sensitive interrupters
edge-sensitive interrupts
ending address register
EPROM socket
EPROM/Flash interface
EPROM/Flash sizing
200/300-Series
400/500-Series
errata sheets, chip
Error Address (Bits 15-8)
Error Address (Bits 23-16)
Error Address (Bits 31-24)
Error Address (Bits 7-4)
error conditions
Error Logger Register
error logging, ECC
error reporting
as a local bus master
as a local bus slave
IndustryPack
IP2 chip
error sources, local
Error Syndrome Register
Ethernet address
Ethernet LAN memory map
Ethernet transceiver interface
examples
generating tick timer periodic interrupt
IP 16-bit memory space
IP 32-bit I/O space
IP 32-bit memory space
IP 8-bit memory space