Motorola MVME172 - Manual (Page 172)

2-94 Computer Group Literature Center Web Site
VMEchip2
2
Interrupt Level Register 3 (bits 0-7)
This register is used to define the level of the software 0 interrupt and the
software 1 interrupt.
SW0 LEVEL These bits define the level of the software 0 interrupt.
SW1 LEVEL These bits define the level of the software 1 interrupt.
Interrupt Level Register 4 (bits 24-31)
This register is used to define the level of the VMEbus IRQ7 interrupt and
the spare interrupt. The VMEbus level 7 (IRQ7) interrupt may be mapped
to any local bus interrupt level.
VIRQ7 LEVEL These bits define the level of the VMEbus IRQ7 interrupt.
SPARE LEVELNot used on the MVME172.
ADR/SIZ $FFF40080 (8 bits [6 used] of 32)
BIT 7 6 5 4 3 2 1 0
NAME SW1 LEVEL SW0 LEVEL
OPER R/W R/W
RESET 0 PSL 0 PSL
ADR/SIZ $FFF40084 (8 bits [6 used] of 32)
BIT 31 30 29 28 27 26 25 24
NAME SPARE LEVEL VIRQ7 LEVEL
OPER R/W R/W
RESET 0 PSL 0 PSL