Motorola MVME172 - Manual (Page 342)

Index
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I
N
D
E
X
block diagram
200/300-Series 1-6
400/500-Series 1-7
VMEchip2 2-5
block diagrams 1-5
block transfer
cycles 2-11
mode 2-9
modes, DMAC 2-59
board
documentation A-1
address, GCSR 2-48
Control Register 2-71 , 2-102
failure 2-71
ID 1-44
Status/Control Register, VMEchip2
2-107
BRDFAIL signal pin 2-71 , 2-72
broadcast interrupt function 2-15
broadcast mode 2-16
BSY signal 2-17
Bus Clock Register 3-38
bus
error 1-48
error handler 1-50
error processing 1-49
map decoder, LCSR 2-20
sizing 2-6
timer enable/disable 2-17
timers, example of use 1-57
byte counter, DMAC 2-61
C
cache coherency 1-48
IP2 chip 4-2
MCECC 5-3
cache inhibit function 1-10
CAS instruction 1-58
cautions 2-102
checksum 1-46
chip arbiter 2-17
chip defaults 5-8
chip ID and revision registers 2-101
Chip ID Register 5-14
Chip ID Register, IP2 chip 4-17
Chip Prescaler Counter 5-25
Chip Revision Register 5-14
Chip Revision Register, IP2 chip 4-17
clear-on-compare mode 2-15
clock programming, IP2 chip 4-43
clocks, VMEchip2 counters and timers 2-68
command chaining mode, DMAC 2-12 , 2-52
command packets, DMAC 2-53
configuration bytes data structure 1-43
cycle type = burst write 5-6
cycle types 5-4
D
data access cycles 2-33 , 2-36
Data Control Register 5-21
data transfer capabilities 2-4 , 2-9 , 2-11
data transfer size 2-11
data transfers 2-43 , 2-44 , 2-52
decoders
programmable 2-4
VMEchip2 2-26
Defaults Register 1 5-34
Defaults Register 2 5-36
devices, normal address range 1-9
DFAIR bit 2-14
direct mode, DMAC 2-52
DMA
Arbitration Control Register, IP2 chip
4-29
Byte Counter, IP2 chip 4-41
control and status register set definition
4-33
Control Register 1, IP2 chip 4-37
Control Register 2, IP2 chip 4-39
Controller (DMAC) 2-10 , 2-52
enable function 4-33
Enable Register, IP2 chip 4-35
IndustryPack Address Counter, IP2 chip
4-41