Motorola MVME172 - Manual (Page 263)

Programming Model
http://www.mcg.mot.com/literature 4-27
4
back I/O and/or ID accesses are ensured if a single size
access is followed by a single size access, or if a double
size, longword access is followed by a single or double
size access. However, if a single size (or byte or word) I/O
or ID access is followed by a double size I/O access, the
double size access may be allowed to happen before the
recovery times for both a and b (or both c and d) have
expired. This behavior is avoided if I/O accesses are
restricted to single size only, or if they are restricted to
double size, longword only and the double size accesses
are not interspersed with ID accesses. Note that memory
accesses do not affect, nor are they affected by, this
behavior.
a_ERR This bit reflects the state of the ERROR* signal from the
IP_a interface.
b_ERR This bit reflects the state of the ERROR* signal from the
IP_b interface.
c_ERR This bit reflects the state of the ERROR* signal from the
IP_c interface.
d_ERR This bit reflects the state of the ERROR* signal from the
IP_d interface.
RT1 RT0
Recovery Time
with IP = 8 MHz
Recovery Time
with IP = 32 MHz
0 0 0 microseconds 0 microseconds
0 1 2 microseconds 0.5 microsecond
1 0 4 microseconds 1 microsecond
1 1 8 microseconds 2 microseconds