Motorola MVME172 - Manual (Page 234)

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MC2 Chip
3
PAREN-PARINT
NONE means no parity checking. Parity errors are not
detected or reported. INTERRUPT means that the MPU
receives a parity interrupt if a parity error occurs. The bus
cycle is terminated with TA*, and runs at the same speed
as unchecked cycles. CHECKED means that the cycle is
terminated by TAE* if a parity error occurs. Note that
CHECKED cycles lengthen the DRAM accesses by one
clock tick.
WWP Setting WWP to a one causes inverted parity to be written
to the DRAM. This is used for diagnostic software.
MPU Status Register
This logic is duplicated in the VMEchip2 at location $FFF40048, bits 11,
10, 9, and 7. The duplication is to enable "No VMEbus Interface"
operation.
PAREN PARINT MPU Alternate
0 0 NONE NONE
0 1 INTERRUPT NONE
1 0 CHECKED CHECKED
1 1 INTERRUPT CHECKED
ADR/SIZ $FFF42048 (8 bits)
BIT 15 14 13 12 11 10 9 8
NAME MCLR MLBE MLPE MLTO
OPER R R R R C R R R
RESET 0 0 0 0 0 PL 0 PL 0 PL 0 PL